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p1/12 pde-2102/12-0.1 high-voltage monolithic ic ecn2102/2112 ecn2102 / 2112 is a single chip row driver ic for electroluminescent (el) display panel. functions * low-voltage serial to high-voltage parallel converter * 34 outputs of totem pole type features * output terminal voltage up to 250v * source / sink current 500ma 34 bit static shift register clk d q1 r1 oe stb vcc vcc q2 r2 q34 r34 so d-ff function block diagram (positive logic) ecn2102 ECN2112 fi g . 1. ou t l ine of f p - 48 package
p2/12 pde-2102/12-0.1 ecn2102/2112 1. general (1) type ecn2102/ECN2112 (2) application row line driver for electroluminecent (el) display panel (3) structure monolithic ic, processed dielectric isolation. ( 4 ) packa g e f p - 48 ( f ig.1) 2. maximum allowable rating (ta=25 c) no items s ymbols ratings units conditions 1 supply voltage (logic) vcc -0.5 ~ +7.0 v to gnd terminal 2 input voltage (logic) vin -0.5 ~ vcc+0.5 v to gnd terminal 3 vs - gnd voltage v sg vcc v to gnd terminal 4 output terminal voltage v q 250 v between vs,vcc,gnd, input and q output 5 allowable power dissipation p t 800 mw 6 operating temperature t op -40 ~ +85 c 7 storage temperature tstg -55 ~ +150 c 3. recommended operating conditions no items s ymbols min. typ. max. units conditions 1 supply voltage (logic) vcc 5.0 5.5 6.0 v 2 clock frequency f clk -- 250 khz vcc= 5.5v 3 clock pulse width tw clk 80 -- ns vin= 0v/5.5v 4 data setup time t su 80 -- ns 5 data hold time t h 80 -- ns 6 output terminal voltage v q - 230 - v vcc= 5.5v 7 peak output source current h ioh -- -500 ma note 1 8 peak output sink current h iol -- +500 ma note 1 note1 : conduction period 5 m s per 1 ic
p3/12 pde-2102/12-0.1 ecn2102/2112 4. electrical characteristics (unless otherwise specified, ta= 25 c, vcc= 5.5v, hvcc=230v) no items symbols min. typ. max. units c o n d i t i o n s 1 output voltage (logic) v ol -- 0.1 v i ol = 20 m a v oh 5.4 -- vi oh =-20 m a 2 output current (logic) i ol 1.0 -- ma v ol = 0.8v i oh -1.0 -- ma v olh 4.7v 3 input voltage (logic) v il -- 1.0 v d input v ih 3.5 -- v v thl -- 0.4 v clk,stb input v tlh 4.5 -- v 4 input current (logic) i ih -- 10 m a vin=5.5v all input/1 input i il -- -10 m a vin=0v d,clk/1 input -- -100 m a vin=0v stb/1 input 5 dissipation current(logic) istb -- 10 m a no signal all input 5.5v, all output off -- 25 ma no signal, 1ch source output on -- 5ma no signal, 1ch sink output on 6 output voltage h vol -- 3.0 v h iol =1ma q out-gnd -- 6.0 v h iol =200ma q out-gnd h voh -- 4.0 v h ioh =-1ma vs-q out -- 8.0 v h ioh =-200ma vs-q out 7 output scr dv/dt capability dv/dt1 200 -- v/ m s vs~q out,+dv/dt apply.fig.6 dv/dt2 200 -- v/ m s q out~gnd,-dv/dt apply.fig.7 8 output scr off period toff -- 6.0 m s source side fig.8 -- 7.0 m ssink side 5. switching characteristics (unless otherwise specified, ta= 25 c, vcc= 5.5v, fig.5) no items symbols min. typ. max. units c o n d i t i o n s 1 output delay time (logic) t plh -- 300 ns cl=15pf t phl -- 300 ns 2 output delay time t qlh -- 3 m srlq=1k w t qhl -- 3 m s clq=2000pf
p4/12 pde-2102/12-0.1 ecn2102/2112 34 bit static shift register clk d q1 ( * ) r1 oe stb vcc vcc q2 r2 q34 r34 so ( * ) : q outputs are "off" at "h" level. d-ff fig. 2. function block diagram (positive logic) 6. function table control input shift register output clk d oe(*4) stb rn so(*1) q shift -* h * shift operation no -* h * keep hh h (*2) output l * hlr34off operation l h l (*3) loff h * h ** all off (*1) 34th data is pushed out as output at the state of down edge of clock signal. (*2) when shift register is "h", source scr of q output is driven to on. (*3) when shift register is "h", sink scr of q output is driven to on. (*4) oe must be kept "h".
p5/12 pde-2102/12-0.1 ecn2102/2112 7. input / output circuit equivalent of each input () pull up vcc input gnd typical of serial output vcc output gnd vcc gnd q output source scr sink scr typical of all q output vs fig. 3. input / output circuit
p6/12 pde-2102/12-0.1 ecn2102/2112 8. example of operating timing chart d ecn2102 clk ECN2112 clk oe h fix. stb vs +hv - hv ( means floating condition.) gnd ecn2102 qn ECN2112 qn ecn2102 qn+1 ECN2112 qn+1 hv : high voltage fig. 4. example of operating timing chart
p7/12 pde-2102/12-0.1 ecn2102/2112 9. measurement and measurement circuit d 50% 50% 50% 50% 10% 90% 10% 90% off on off on off off on off on off sw1 oe clk stb t qlh t qhl t qlh t qhl other q output q1 q2 h fix. sw2 (b) output function (sw3 ? off) clk d oe stb vcc vs sw1 250v sw2 rlq clq sw3 cl measurement point rlq=1k w clq=2000pf cl=15pf 5.5v q1 q2 q34 so gnd fig. 5. switching characteristics measurement circuit 1/f clk t wclk tsu th 50% 50% 50% 50% 50% t1 t2 t34 tn : figure n means n th pulse plh t phl t clk d so 50% t ilh 90% input condition t ihl , =10ns typ. 10% 5.5v 0v t ilh t ihl (a) shift function (sw1 ? off, sw2,3 ? on)
p8/12 pde-2102/12-0.1 ecn2102/2112 clk d oe stb vcc vs 5.5v q1 q2 q34 so gnd 1000pf 1k w +dv/dt pulser (to reach 150v) fig. 6. output scr dv/dt capability (dv/dt1) measurement circuit clk d oe stb vcc vs 5.5v q1 q2 q34 so gnd 1000pf 1k w -dv/dt pulser (to reach -150v) fig. 7. output scr dv/dt capability (dv/dt2) measurement circuit
p9/12 pde-2102/12-0.1 ecn2102/2112 clk d oe stb vcc vs 5.5v qn so gnd io ? clk h fix. h fix. 100ma min 150v dv/dt @ 100v/ m s toff d oe stb vs io scr off scr on b y mistake 12 34 (a) source scr clk d oe stb vcc vs 5.5v qn so gnd io ? clk h fix. l fix. 100ma min 150v dv/dt @ 100v/ m s toff d oe stb vs io scr off scr on by mistake 12 34 (b) sink scr fig. 8. output scr toff measurement
p10/12 pde-2102/12-0.1 ecn2102/2112 10. pin location q34 q33 q32 q31 q30 q29 q28 q27 q26 q25 q24 q23 q22 q21 q20 q19 q18 vs gnd (nc) (nc) vcc stb so q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 vs gnd (nc) (nc) oe clk d (a) ecn2102 q34 q33 q32 q31 q30 q29 q28 q27 q26 q25 q24 q23 q22 q21 q20 q19 q18 vs gnd (nc) (nc) vcc stb so q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 vs gnd (nc) (nc) oe clk d (b) ECN2112 fig. 9. pin location (top view)
p11/12 pde-2102/12-0.1 ecn2102/2112 11. package outline (unit : mm) (1) ecn2102 surface note 2 note 1 note 5 18.8 0.4 0.35 0 . 1 14.0 0.2 20.0 typ. 2.40 typ. 1.20 0.20 0 - 10 3.05 max. note 3 0.15 0.05 1.25 typ. 0.8 0 . 1 5 9.2 0.3 note 1 9.2 0.3 note 1 notes. 1. this dimension is measured at root of lead. spacing at tip of lead is min 0.2. 2. this dimension includes a warpage of package. 3. marking is on the surface of package, including hitachi mark, type name, lot number, and japan mark. 4. leads are solder plated. 5. this is the bending angle with horizontal plane. fig. 10. package outline (ecn2102)
p12/12 pde-2102/12-0.1 ecn2102/2112 (unit : mm) (2) ECN2112 surface note 2 note 1 note 5 18.8 0.4 0.35 0 . 1 14.0 0.2 20.0 typ. 2.40 typ. 1.20 0.20 0 - 10 3.05 max. note 3 0.15 0.05 1.25 typ. 0.8 0 . 1 5 9.2 0.3 note 1 9.2 0.3 note 1 notes. 1. this dimension is measured at root of lead. spacing at tip of lead is min 0.2. 2. this dimension includes a warpage of package. 3. marking is on the surface of package, including hitachi mark, type name, lot number, and japan mark. 4. leads are solder plated. 5. this is the bending angle with horizontal plane. fig. 11. package outline (ECN2112)
1. the information given herein, including the specifications and dimensions, is subject to change without prior notice to improve product characteristics. before ordering, purchasers are adviced to contact hitachi sales department for the latest version of this data sheets. 2. please be sure to read "precautions for safe use and notices" in the individual brochure before use. 3. in cases where extremely high reliability is required(such as use in nuclear power control, aerospace and aviation, traffic equipment, life-support-related medical equipment, fuel control equipment and various kinds of safety equipment), safety should be ensured by using semiconductor devices that feature assured safety or by means of users? fail-safe precautions or other arrangement. or consult hitachi?s sales department staff. 4. in no event shall hitachi be liable for any damages that may result from an accident or any other cause during operation of the user?s units according to this data sheets. hitachi assumes no responsibility for any intellectual property claims or any other problems that may result from applications of information, products or circuits described in this data sheets. 5. in no event shall hitachi be liable for any failure in a semiconductor device or any secondary damage resulting from use at a value exceeding the absolute maximum rating. 6. no license is granted by this data sheets under any patents or other rights of any third party or hitachi, ltd. 7. this data sheets may not be reproduced or duplicated, in any form, in whole or in part , without the expressed written permission of hitachi, ltd. 8. the products (technologies) described in this data sheets are not to be provided to any party whose purpose in their application will hinder maintenance of international peace and safety not are they to be applied to that purpose by their direct purchasers or any third party. when exporting these products (technologies), the necessary procedures are to be taken in accordance with related laws and regulations. hitachi power semiconductors ? for inquiries relating to the products, please contact nearest overseas representatives which is located ?inquiry? portion on the top page of a home page. notices notices notices notices hitachi power semiconductor home page address http://www.hitachi.co.jp/pse

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